The invention relates to radio navigation and, more specifically, it relates to digital correlators of receivers used for reception of the pseudo-noise signals of the satellite radio navigation systems (SRNS) GPS (USA) and GLONASS (Russia) performing simultaneous reception of the signals of the C/A codes of these systems in the L1 frequency range.
The receivers of pseudo-noise (noise-like) signals of the SRNS GLONASS (cf. xe2x80x9cGlobal Navigational Satellite Systemxe2x80x94GLONASS. Interface Control Document. KNITS VKS Russia xe2x80x9d, 1995) [1] and GPS (cf. xe2x80x9cGlobal Position System. Standard Positioning Service. Signal Specification.xe2x80x9d USA, 1993) [2] are now widely used for establishing the coordinates (latitude, longitude, height), speed of objects, and time. The fundamental distinctions between the SRNS GPS and the GLONASS consist in the use of different, although adjacent, frequencies on the L1 band, use of different pseudo-noise modulating codes and use of both code and frequency division of signals of the different satellites in the system. Thus, during operation on the L1 frequency band the SRNS GPS satellites transmit signals modulated by different pseudo-noise codes on one carrier frequency 1575.42 MHz while the SRNS GLONASS satellites transmit signals modulated by the same pseudo-noise code on different carrier (letter) frequencies laying in the adjacent frequency zone.
The distinctions existing between the SRNS GPS and GLONASS signals stipulated by the code division in the SRNS GPS and the frequency division in the SRNS GLONASS result in different hardware used for reception and correlation processing of these SRNS signals to allow one to carry out the radio navigation measurements.
The typical SRNS receiver operates with a complex noise-like signal (NLS) consisting of a plurality of radio signals radiated by the SRNS satellites, a noise component, as well as a component due to the interference caused by the repeated reflection of the signals from various surface areas, buildings, etc.
Known in the art is a SRNS GPS receiver of pseudo-noise signals (cf. FIG. 1 in the xe2x80x9cGlobal Positioning System (GPS) Receiver RF Front End. Analog-Digital Converterxe2x80x9d, Rockwell International Proprietary Information Order Number. May 31, 1995) [3], comprising a radio-frequency converter including a low-noise amplifier, a filter, a first mixer, a first intermediate frequency amplifier, a quadrature mixer, two quantizers for the inphase and quadrature channels, a signal shaper producing a first heterodyne frequency (1401.51 MHz), a divider producing a signal of a second heterodyne frequency from the signal of the first heterodyne frequency, and a correlation processing unit. The device solves a technical problem of reception and correlation processing of the SRNS GPS signal for the purpose of consequent radio navigation measurements, however, it does not allow one to solve the problem of reception and correlation processing of the SRNS GLONASS signals.
Also known in the art (cf. FIG. 9.2 on pages 146-148 in the book xe2x80x9cNetwork Satellite Systemsxe2x80x9d, by V. S. Shebshaevich, P P. Dmitriev, N. V. Ivantsevich, et all. Moscow, xe2x80x9cRadio i Syazxe2x80x9d, 1993)[4] a receiver of the SRNS GLONASS pseudo-noise signals (xe2x80x9cSingle-Channel Users"" Equipment xe2x80x98ACH-37xe2x80x99 for the GLONASS Systemsxe2x80x9d). The receiver comprises an antenna, a low-noise amplifier/converter, a radio-frequency converter, a digital processing device, and a navigational processor. The low-noise amplifier/converter includes band-pass filters, an amplifier and a mixer. The radio-frequency converter includes an amplifier, a phase demodulator, a second mixer, a limiter and a lettered frequency synthesizer operating on the signals of a reference generator. The device includes a pseudorandom sequence generator (PSG) with a digital clock-signal generator of the PSG, a digital Doppler carrier drift generator, and a phase-code converter with a storage unit for storing the digital samples. The lettered frequency synthesizer generates output signals according to the lettered frequencies of the received SRNS GLONASS signals. The spacing of the lettered frequencies generated by the synthesizer is equal to 0.125 MHz. The first heterodyne frequency signal is produced by multiplying the synthesizer output signal by four while the second heterodyne frequency signal is produced by dividing the frequency at the output of the frequency synthesizer by two. The receiver solves the technical problem of reception and correlation processing of the SRNS GLONASS signals to provide the consequent radio navigation measurements and positioning, however, it does not allow one to solve the problem of reception and correlation processing of the SRNS GPS signals.
In spite of the difference existing between the SRNS GPS and GLONASS, their similarity on designation, ballistic build-up of the orbital groups of satellites and used frequency range allows one to formulate and solve the problems associated with the creation of the receivers capable of processing the signals of these two systems. The result achieved consists in a high reliability, authenticity and accuracy of defining the location of an object, in particular, due to a possibility of selecting a working constellations of satellites with the best geometrical parameters [4, page 160].
Known in the art among the devices performing the reception and correlation processing of the SRNS GPS and GLONASS signals is a receiver of SRNS GPS and GLONASS signals operating in the L1 frequency range, described in ([4], page 158-161, FIG. 9.8). The receiver comprises an antenna, a radio-frequency converter, a reference generator and a processor for primary processing. The radio-frequency converter comprises a dupleyer performing frequency division of the SRNS GPS and GLONASS signals, band-pass filters and amplifiers of the GPS and GLONASS channels, a mixer, a switch applying the SRNS GPS or GLONASS signals to the signal input of the mixer, a switch applying the first heterodyne signal to the reference input mixer for the GPS channel or the GLONASS channel. Due to the respective frequency shaping of the heterodyne signal, the first intermediate frequency is constant for the SRNS GPS and GLONASS signals and all subsequent operations of signal processing are common for both systems. The processor for primary signal processing includes a multiplexer with a ROM unit, a digital generator of lettered frequencies, a digital correlator, a PSG generator and a microprocessor. A disadvantage of this device is that the reception, conversion and correlation signal processing of each SRNS is carried out in sequence.
Also known in the art is a receiver of the SRNS GPS and GLONASS signals in the L1 frequency range (cf. xe2x80x9cRiley S., Howard N., Aardoom E., Daly P., Silvestrin P. xe2x80x9cA Combined GPS/GLONASS High Precision Receiver for Space Applicationsxe2x80x9d, Palm Springs, CA, US, Sept. 12-15, 1995, pp.835-844) [5], which solves the problem of simultaneous reception of signals of both types of SRNS and the parallel correlation processing of these signals. The receiver of SRNS signals described in [5] comprises an antenna, a radio-frequency converter with a digitizer and N digital correlators connected in series. The receiver described in [5], performs procedures of reception, search (detection) and tracing of signals typical for the SRNS receivers. These procedures consist in the following. For detection, tracing and determination of parameters of the received SRNS signals, these signals are amplified, converted into IF-signals and digitized in the radio-frequency unit of the receiver and, finally, the signals are demodulated using the digital correlation technique in the N correlators processing the signals of individual SRNS satellites. The typical procedures performed by the digital correlator of the SRNS signal receiver consist in correlation of the received NLS signal by multiplying its digital readouts by the local copy of the sought signal generated inside the correlator, and storage of the correlation results during a definite time spacing. As a rule, this spacing is 1 millisecond, that is equal to the length of the pseudorandom code sequence (PSG) of C/A code of the SRNS GPS and GLONASS. The closure of the loop of tracing the frequency (phase) and delay of the PSG code of the satellite SRNS signal being processed is carried out with the help of a processor. The processor reads out the information from the respective memory of the correlator, processes the information with the help of suitable programs and produces feedback control signals thus closing the tracing loops. In so doing, to perform the code tracing (code delay), use is made of the results of correlation of the input signal with early (advance) and late (delayed) copies of the input signal, or with a difference (early-minus-late) copy. The procedure of tracing the code (code delay) is used at the initial step of search (detection) of the signal. The search (detection) of signals in the SRNS receiver is carried out by two parameters: delay and frequency. The combination of positions of search by frequency and delay defines a search area (FIG. 1). Depending on an apriori information on the Doppler frequency shift, the structure of the systems for tracing the frequency and delay, reference generator stability and other parameters, number of positions of searching by frequency can vary in a wide range from one position up to several dozens. The number of positions by delay is determined by the spacing of uncertainty and in the worst case is equal to double the number of PSG digits per period. The search of signals in the SRNS receiver is carried out under conditions of a wide dynamic range of change of the input signal power level. This range depends on the location of the SRNS satellite, propagation losses, type of the directional pattern and other additional factors. In fact, the range of change of the power of the input signals of the SRNS receivers is within 25 dB. The process of searching the signal of an SRNS satellite realized in the digital correlator of the SRNS signal receiver consists of a sequential selection of all positions of the search area (FIG. 1) and comparison with a given detection threshold, which is determined stemming from the given probabilities of the skip and false alarm, thus the detection threshold is calculated based on the least signal level. The decision on the absence or presence of a signal in a given position is based on the results of study of a concrete position (FIG. 1).
A traditional decision is that the storage (at a spacing of 1 ms) in the digital correlator of the SRNS receiver is effected by means of hardware, and the decision on the presence or absence of a signal is made by the processor, i.e. at a software level. The digital correlator of the receiver of the SRNS GPS and GLONASS signals, making such a decision and described in [5], is taken as a prior art. The block diagram of the prior art system is shown in FIG. 2.
The digital correlator of the SRNS signal receiver, chosen as a prior art, comprises (FIG. 2) a switch 1 for switching the input signals, a data exchange unit 2, a processor 3, a first 4, a second 5, a third 6 and a fourth 7 storage units; a digital carrier generator 8; a control register 9; a digital code generator 10; a generator 11 of reference C/A code of the SRNS GPS/GLONASS; a programmable delay line 12; a first 13 and a second 14 digital mixers, respectively, of the inphase and quadrature channels of correlation processing; a first 15, a second 16, a third 17 and a fourth 18 demodulators. The first and second signal inputs of the input signals switch 1 (the inputs GPS and GLONASS) constitute signal inputs of the digital correlator. The clock inputs of the storage units 4-7, of the digital code generator 10, of the digital carrier generator 8 and of the programmable delay line 12 form a clock input of the digital correlator. The signal inputs of the digital correlator (i.e. the signal inputs of the switch 1) are connected to the outputs of the radio-frequency converter (not shown in FIG. 2), in which the received SRNS GPS and GLONASS signals are converted into a second intermediate frequency, the signals are subjected to 4-bit analog-to-digital conversion at a clock frequency of FT=57.0 MHz (4xc3x9714.25 MHz), and two-bit samples of the inphase (I) and quadrature (Q) components of the SRNS GPS and GLONASS signals are shaped with a sampling rate twice as low as FT, i.e. equal to 28.5 MHz (2xc3x9714.25 MHz), where 14.25 MHz is the average frequency of SRNS GPS and GLONASS signals on the second intermediate frequency. The digital correlator clock input is connected to the signal output FT/2 of the radio-frequency converter. The data exchange unit 2 is connected through data buses to the processor 3, to the outputs of the storage units 4-7, and to the control inputs of the digital carrier generator 8, control register 9, digital code generator 10 and reference generator 11 of the C/A code of the SRNS GPS and GLONASS. The control input of the input signal switch 1 is connected to the first output of the control register 9, and the switch output is connected to the first inputs of the digital mixers 13 and 14 of the inphase and quadrature channels of correlation processing. The second inputs of the digital mixers 13 and 14 are connected respectively to the xe2x80x9ccosinexe2x80x9d and xe2x80x9csinexe2x80x9d outputs of the digital carrier generator 8 while the outputs are connected to the junction between the first inputs of the first 15 and second 16 demodulators and to the junction between the first inputs of the third 17 and fourth 18 demodulators whose outputs are connected respectively to the signal inputs of the first 4, second 5, third 6 and fourth 7 storage units. The second inputs of the first 15 and fourth 18 demodulators are connected to the output of the punctual (exact) xe2x80x9cPxe2x80x9d copy of the reference C/A code of the programmable delay line 12. The second inputs of the second 16 and third 17 demodulators are connected to the output of the difference xe2x80x9cE-Lxe2x80x9d copy or the early xe2x80x9cExe2x80x9d copy of the reference C/A code of the programmable delay line 12. The signal input of the programmable delay line 12 is connected to the output of the generator 11 of the reference C/A code of the SRNS GPS and GLONASS, whose signal input is connected to the output of the digital code generator 10. The control input of the generator 11 of the reference C/A code of the SRNS GPS and GLONASS C/A radio navigation systems and the control input of the programmable delay line 12 are connected, respectively, to the first and second outputs of the control register 9. The digital correlator of the SRNS signal receiver, accepted as a prior art operates as follows. Applied to the GPS and GLONASS inputs of the switch 1 switching the input signals 4 are two-bit samples (I) and quadrature (Q) components of the SRNS GPS and GLONASS signals, respectively, at a sampling rate of FT/2 (28.5 MHz). Following the command of the processor 3 transmitted to the control register 9 through the data exchange unit 2, the switch 1 of the input signals 4 connects to its output the two-bit quadrature signals (I and Q) of the SRNS GPS or GLONASS. These signals are applied to the first inputs of the digital mixers 13 and 14 whose second inputs are fed with the signals xe2x80x9cCOSxe2x80x9d and xe2x80x9cSINxe2x80x9d at a reference frequency from the respective outputs of the digital carrier generator 8. The digital carrier generator 8 generates xe2x80x9cSINxe2x80x9d and xe2x80x9cCOSxe2x80x9d signals of the intermediate frequency of a given SRNS GLONASS letter, whose binary code is given by the processor 3, or of the intermediate frequency of SRNS GPS signals. With the sampling rate of FT/2 =28.5 MHz, the values of intermediate frequencies of the SRNS GPS or GLONASS signals laying in a range of 14.25 MHz. The digital mixers 13 and 14 recover the signals of a given letter of the SRNS GLONASS signals or the satellites SRNS GPS signals and transfer the spectra of these signals into the fundamental frequency band (on a zero-point frequency). From the outputs of the digital mixers 13 and 14 signals are applied to the first inputs of the demodulators 15, 16 and 17, 18. Applied to the second inputs of the demodulators 15, 18 and 16, 17 are the punctual copy xe2x80x9cPxe2x80x9d and difference copy xe2x80x9cE-Lxe2x80x9d (Early-Late) or early copy xe2x80x9cExe2x80x9d. The digital demodulators 15, 18 and 16, 17 perform correlation of the received signals with punctual (exact) xe2x80x9cPxe2x80x9d and difference xe2x80x9cE-Lxe2x80x9d (Early-Late) or early xe2x80x9cExe2x80x9d copies of the reference C/A code of the SRNS GPS or GLONASS respectively. These copies of the code are produced by the programmable delay line 12, which allows the spacing between the early and late copies of the C/A code to be changed from 0.1 to 1 length of the digit of the C/A code and, therefore, to shape a xe2x80x9cnarrow discriminatorxe2x80x9d in the system for tracing the code of the SRNS receiver. The programmable delay line 12 responses to the signals fed from the output of the reference C/A code generator 11 of the SRNS GPS/GLONASS, shaping reference pseudorandom C/A codes of the SRNS GPS or GLONASS satellites. The signal of a clock rate 1.023 MHz necessary for operation of the generator 11 of the GPS or 0.511 MHz for the GLONASS is applied to its signal input from the output of the digital code generator 10. The selection of the produced pseudorandom code sequence and the code clock rate values is carried out by the commands of the processor 3 transmitted through the data exchange unit 2. The results of correlation of the signals are stored in the storage units 4-7. For the case of operation with punctual and difference copies of an input signal the unit 4 stores the quadrature component of correlation of the punctual copy of a signal Qp, the unit 5 stores the quadrature component of correlation of the difference copy Qd, the unit 7 stores the inphase component of the punctual copy Ip, the unit 6 stores the inphase component of the difference copy Id. The data stored in the storage units 4-7 are periodically read out by means of the data exchange unit 2 controlled by the processor 3, in which are realized all algorithms of signal processing, i.e. algorithms of searching the signals, tracing the carrier code, and receiving the service information. The storage period is equal to the C/A code period, i.e. to 1 ms. Using the signal processing results, the processor 3 controls the digital correlator, giving out the carrier frequency estimated values to the digital carrier generator 8 and the sending the code clock rate to the digital code generator 10.
Thus, the data storage at a 1 ms spacing is effected by the hardware in the digital correlator of the SRNS signal receiver, taken as a prior art, while the decision on the presence or absence of a signal is made by the processor 3, i.e. on the software basis.
The use of the given structure is expedient for the navigational equipment, in which all operational resources of the calculator (processor) are used for solving the purely navigational problemsxe2x80x94positioning by means of the SRNS satellites signals, which is performed in the SRNS receiver described in [5]. However, such a solution does not allow one to render additional services to the user, for example, it is not suitable for a design of a small-size cellular telephone equipped with an element for emergency announcement of an extreme situation with transmission of the location data.
The technical result to be achieved by this invention is a use of one calculator (processor) both for solving the problem of location and maintenance of communication by unloading the processor of the digital correlator of the SRNS signal receiver, when searching the signals by using an additional operation of xe2x80x9cfast searchxe2x80x9d in the correlator hardware. For example, under conditions of transmission of an emergency message the processor should process the navigational information (to perform the search of the signals and make radio navigation measurements), as well as to generate and transmit the communication information (to perform xe2x80x9cconversation processingxe2x80x9d) and also to control the transmitted message, etc.). To realize such a mode, the processor operation should be optimized (processor should be xe2x80x9cunloadedxe2x80x9d). In a majority of real cases of solving the navigational problem, the time of search of the SRNS signals is reduced, the processor is unloaded and can be used for performing other tasks, for example, those associated with the integration.
According to the present invention a digital correlator of the signal receiver of satellite radio navigational systems (SRNS)includes a switch for switching the input signals, whose inputs form signal inputs of the digital correlator, a data exchange unit connected through a suitable data bus to the processor and to the outputs of a first, a second, a third and a fourth storage units controlling the inputs of a digital carrier generator, a digital code generator, and a reference C/A code generator of the SRNS GPS/GLONASS system. The clock inputs of the storage units, of the digital code generator, of the digital carrier generator and of the programmable delay line form a clock input of the digital correlator. The control input of the switch is connected to the first output of the control register. The output of the input signal switch is connected to the first inputs of the first and second digital mixers, respectively, of the inphase and quadrature correlation processing channels whose second inputs are connected, respectively, to the xe2x80x9ccosinexe2x80x9d and xe2x80x9csinexe2x80x9d outputs of the digital carrier generator. The outputs of the first and second digital mixers are connected to the junction between the first inputs of the first and second demodulators and to the junction between the first inputs of the third and fourth demodulators whose outputs are connected, respectively, to signal inputs of the first, second, third and fourth storage unit. The second inputs of the first and fourth demodulators are connected to the output of the punctual (exact) copy xe2x80x9cPxe2x80x9d of the reference C/A code of the programmable delay line, the second inputs of the second and third demodulators are connected to the output of the difference xe2x80x9cE-Lxe2x80x9d or early xe2x80x9cExe2x80x9d copy of the reference C/A code of the programmable delay line, the signal input of the programmable delay line is connected to the output of the reference C/A code generator of the SRNS GPS/GLONASS, the generator signal input being connected to the output of the digital code generator; the control input of the reference C/A code generator of the SRNS GPS/GLONASS and the control input of the programmable delay line being connected, respectively, to the first and second outputs of the control register. According to the present invention, the digital correlator further comprises first and second decision making units whose control inputs and outputs are connected through suitable buses to the data exchange unit. The first and second signal inputs of the first decision making unit are connected, respectively, to the outputs of the second and third storage units. The first and second signal inputs of the second decision making unit are connected, respectively, to the outputs of the first and fourth storage units. In a preferred embodiment of the invention, each decision making unit comprises: first and second modulus determining deices whose inputs form, respectively, first and second signal inputs of the decision making unit; an adder whose inputs are connected to the outputs of modulus determining devices; a threshold register whose input forms a control input of the decision making unit; a first, a second and a third threshold devices, whose signal inputs are connected, respectively, to the output of the adder and to the outputs of the first and second modulus determining devices; the reference input of the first threshold device is connected to the first output of the threshold register, the reference inputs of the second and third threshold devices are connected to the second output of the threshold register, the outputs of the threshold devices through an xe2x80x9cORxe2x80x9d circuit are connected to the input of the output register whose output is in fact the output of the decision making unit.